* tWRPRE κ°’ 계산이 λ‹€λ₯Ό 수 있음, μžμ„Έν•œ λ‚΄μš©μ€ μ•„λž˜μ—





μ›λž˜λŠ” 2개 μ •λ„λ§Œ κ³¨λΌμ„œ κΈ€ μ“°λ €κ³  ν–ˆλŠ”λ°

램 타이밍 κ³„μ‚°ν•΄λ³΄λ‹ˆκΉŒ 7200, 7400, 7600 λ‹€ λΉ„μŠ·ν•˜κ²Œ 타이밍 계산이 λ˜λ”λΌκ³ 




κ·Έλž˜μ„œ κ·Έλƒ₯ 7200 - 7600 λ¬Άμ–΄μ„œ ν•œ λ²ˆμ— μ •λ¦¬ν•˜λ €κ³  함

λ©€ ν…ŒμŠ€νŠΈλŠ” 7600 CL32둜 μ§„ν–‰ν–ˆκ³ , μ•„λ§ˆ 7200, 7400에 λ™μΌν•˜κ²Œ 적용 κ°€λŠ₯ν•  κ²ƒμœΌλ‘œ 생각됨



참고둜 λͺ¨λ“  ν…ŒμŠ€νŠΈλŠ” μ΅œμ‹  λ°”μ΄μ˜€μŠ€, Intel Default Settings μ μš©ν•΄μ„œ 진행함






!! μ£Όμ˜ν•  점 !!

쀀비물은 ν•˜μ΄λ‹‰μŠ€ A 닀이 램 16GB * 2


VDD, VDDQ λŠ” 램 수율 많이 νƒˆκ±°μž„

λ‚΄ λž¨μ€ 8000 CL34 κΈ°μ€€μœΌλ‘œ 1.46 V μ•ˆμ •ν™” λ¬μ—ˆλ˜ 램이고

이번 7600 CL32 램 전압은 8000 CL34 κΈ°μ€€ 1.48 V 둜 작고 κ³„μ‚°ν–ˆμŒ


보톡 μ‹œκΈˆμΉ˜ μ „μ•• 수율 γ…γ…Œγ…Š λŠ” 8000 CL34 κΈ°μ€€ 1.56 - 1.58 V

νŠœλ‹λž¨ μ „μ•• μˆ˜μœ¨λ„ μ‹œκΈˆμΉ˜λž‘ λΉ„μŠ·ν•¨


κ·ΈλŸ¬λ‹ˆ, μ „μ•• μ„ΈνŒ…μ€ 본인 램 μˆ˜μœ¨μ΄λ‚˜ μž₯λΉ„ μƒνƒœ 보고 μ μš©ν•˜λ„λ‘ ν•˜μž






μ „μ•• μ„ΈνŒ…


1. 7600 CL32


SA 1.25 V (AUTO)

VDD 1.58 - 1.50 V

VDDQ 1.58 - 1.50 V

CPU VDD2 (Memory Controller, MC) 1.48 - 1.45 V

CPU VDDQ (Transmitter, Tx) 1.35 V (AUTO)



2. 7400 CL32


SA 1.25 V (AUTO)

VDD 1.54 - 1.46 V

VDDQ 1.54 - 1.46 V

CPU VDD2 (Memory Controller, MC) 1.46 - 1.43 V

CPU VDDQ (Transmitter, Tx) 1.35 V (AUTO)



3. 7200 CL32


SA 1.25 V (AUTO)

VDD 1.50 - 1.42 V

VDDQ 1.50 - 1.42 V

CPU VDD2 (Memory Controller, MC) 1.45 - 1.40 V

CPU VDDQ (Transmitter, Tx) 1.35 V (AUTO)




μ„ΈλΆ€ 램 타이밍


tCL 32

tRCD 44

tRCDWR 44

tRP 44

tRAS 30 - 32


tRRD_L 8

tRRD_S 4



tRFC2 (120 ns / 130 ns / 140 ns / 150 ns / 160 ns / 170 ns)

ν•˜μ΄λ‹‰μŠ€ A 닀이: 120, 130 ns

ν•˜μ΄λ‹‰μŠ€ M 닀이: 160+ ns


- 7600 > 456 / 494 / 532 / 570 / 608 / 646

- 7400 > 444 / 481 / 518 / 555 / 592 / 629

- 7200 > 432 / 468 / 504 / 540 / 576 / 612


tRFCsb (tRFC2 - 30 ns)

ν•˜μ΄λ‹‰μŠ€ A 닀이: 100+ ns

ν•˜μ΄λ‹‰μŠ€ M 닀이: 130+ ns


- 7600 > 380 (100 ns), 494 (130 ns)

- 7400 > 370 (100 ns), 481 (130 ns)

- 7200 > 360 (100 ns), 468 (130 ns)


tREFI

- 65535: 램 μ˜¨λ„ 50도 μ΄ˆλ°˜κΉŒμ§€λ„ γ…‡γ…‹

- 131071: 램 μ˜¨λ„ μ•½ 45도 κΉŒμ§€

- 262143: 램 μ˜¨λ„ μ•½ 35도 λ‚΄μ™Έ (사싀상 컀수 μ „μš©)



tWR

μžλ™ 계산 적용 (10)

(tWRPDEN = tCWL + tWR + 8)

(tWR = tWRPDEN - tCWL - 8)



tRTP 12


tFAW 16


tCWL 28

(tCWL = tCL - 2)


tCKE 10



tWTR_L

μžλ™ 계산 적용 (24)

(tWRRD_sg = tCWL + tWTR_L + 6)

(tWTR_L = tWRRD_sg - tCWL - 6)


tWTR_S

μžλ™ 계산 적용 (12)

(tWRRD_dg = tCWL + tWTR_S + 6)

(tWTR_S = tWRRD_dg - tCWL - 6)



tRDRD_sg 16


tRDRD_dg 8


tRDWR_sg 20


tRDWR_dg 20


tWRWR_sg 12


tWRWR_dg 8


tWRRD_sg 60

tWTR_L λ°”κΏ€ λ•Œ 이 값을 λ°”κΏ”μ€˜μ•Ό 함

(tWRRD_sg = tCWL + tWTR_L + 6)


tWRRD_dg 48

tWTR_S λ°”κΏ€ λ•Œ 이 값을 λ°”κΏ”μ€˜μ•Ό 함

(tWRRD_dg = tCWL + tWTR_S + 6)



tRDRD_dr 1 (λ³΄λ“œμ— λ”°λΌμ„œ μ΅œμ†Ÿκ°’ 4)

tRDRD_dd 1 (λ³΄λ“œμ— λ”°λΌμ„œ μ΅œμ†Ÿκ°’ 4)

tRDWR_dr 1 (λ³΄λ“œμ— λ”°λΌμ„œ μ΅œμ†Ÿκ°’ 4)

tRDWR_dd 1 (λ³΄λ“œμ— λ”°λΌμ„œ μ΅œμ†Ÿκ°’ 4)

tWRWR_dr 1 (λ³΄λ“œμ— λ”°λΌμ„œ μ΅œμ†Ÿκ°’ 4)

tWRWR_dd 1 (λ³΄λ“œμ— λ”°λΌμ„œ μ΅œμ†Ÿκ°’ 4)

tWRRD_dr 1 (λ³΄λ“œμ— λ”°λΌμ„œ μ΅œμ†Ÿκ°’ 4)

tWRRD_dd 1 (λ³΄λ“œμ— λ”°λΌμ„œ μ΅œμ†Ÿκ°’ 4)



tWRPRE 47 λ˜λŠ” 49 *

μ‚¬μš©ν•˜λŠ” λ©”μΈλ³΄λ“œ, λž¨μ— 따라 계산 방법이 닀름

μˆœμ • κ°’Β λ˜λŠ” auto κ°’ 확인 ν›„ μ μš©ν•  것

(tWRPRE = tWRPDEN - 1 orΒ tWRPDEN + 1)


tWRPDEN 48

tWR λ°”κΏ€ λ•Œ 이 값을 λ°”κΏ”μ€˜μ•Ό 함

(tWRPDEN = tCWL + tWR + 8)



와 인텔은 λ­” κ³„μ‚°ν• κ²Œ 이래 λ§Žλƒ γ…‹γ…‹γ…‹γ…‹






μ–΄μ§Έλ“  끝