* tWRPRE ๊ฐ’ ๊ณ„์‚ฐ์ด ๋‹ค๋ฅผ ์ˆ˜ ์žˆ์Œ, ์ž์„ธํ•œ ๋‚ด์šฉ์€ ์•„๋ž˜์—



์ด๋ฒˆ์—๋Š” ๋‚œ์ด๋„ ์กฐ๊ธˆ ์™„ํ™”๋œ 7600 CL34 ๋ฒ„์ „์ž„

์•„๋ž˜ 7600 CL32 ๊ฒฐ๊ณผ๋ž‘ ๋น„๊ตํ•ด๋ณด๋ฉด ์„ฑ๋Šฅ ์ฐจ์ด ๊ต‰์žฅํžˆ ์ ์–ด๋ณด์ž„



7600 CL32 ์ •๋ณด๊ธ€

https://gall.dcinside.com/m/desktopcomputer/3603



๋น„๊ตํ•ด๋ณด๋ฉด ์„ฑ๋Šฅ ์ฐจ์ด ์ง„์งœ ์–ผ๋งˆ ์•ˆ๋‚˜๋ณด์ด๋Š”๋ฐ

์ „์•• ์š”๊ตฌ๋Ÿ‰๋„ ํ™• ์ค„์–ด์„œ tCL 2 ์ฐจ์ด์— ๋ชฉ๋ฉ”์ง€ ๋ง๊ณ  CL34 ์จ๋„ ใ„ฑใ…Š ํ• ๋“ฏ


ํ…Œ์ŠคํŠธ ํ•œ VDD ์ „์•• ์ฐจ์ด๋Š” CL32 1.50 V v.s. CL34 1.42 V ์ž„ ใ…‹ใ…‹ใ…‹ใ…‹ใ…‹ใ…‹ใ…‹



๋ชจ๋“  ํ…Œ์ŠคํŠธ๋Š” ์ตœ์‹  ๋ฐ”์ด์˜ค์Šค, Intel Default Settings ์ ์šฉํ•ด์„œ ์ง„ํ–‰ํ•จ




์ „์•• ์„ธํŒ…


SA 1.25 V (AUTO)

VDD 1.50 - 1.42 V

VDDQ 1.50 - 1.42 V

CPU VDD2 (Memory Controller, MC) 1.45 - 1.40 V

CPU VDDQ (Transmitter, Tx) 1.35 V (AUTO)




์„ธ๋ถ€ ๋žจ ํƒ€์ด๋ฐ


tCL 34

tRCD 44

tRCDWR 44

tRP 44

tRAS 32 - 34


tRRD_L 8

tRRD_S 4



tRFC2 (120 ns / 130 ns / 140 ns / 150 ns / 160 ns / 170 ns)

ํ•˜์ด๋‹‰์Šค A ๋‹ค์ด: 120, 130 ns

ํ•˜์ด๋‹‰์Šค M ๋‹ค์ด: 160+ ns


456 / 494 / 532 / 570 / 608 / 646


tRFCsb

ํ•˜์ด๋‹‰์Šค A ๋‹ค์ด: 100+ ns

ํ•˜์ด๋‹‰์Šค M ๋‹ค์ด: 130+ ns


380 (100 ns), 494 (130 ns)



tREFI

- 65535: ๋žจ ์˜จ๋„ 50๋„ ์ดˆ๋ฐ˜๊นŒ์ง€๋„ ใ…‡ใ…‹

- 131071: ๋žจ ์˜จ๋„ ์•ฝ 45๋„ ๊นŒ์ง€

- 262143: ๋žจ ์˜จ๋„ ์•ฝ 35๋„ ๋‚ด์™ธ (์‚ฌ์‹ค์ƒ ์ปค์ˆ˜ ์ „์šฉ)



tWR

์ž๋™ ๊ณ„์‚ฐ ์ ์šฉ (10)

(tWRPDEN = tCWL + tWR + 8)

(tWR = tWRPDEN - tCWL - 8)



tRTP 12


tFAW 16


tCWL 32

(tCWL = tCL - 2)


tCKE 10



tWTR_L

์ž๋™ ๊ณ„์‚ฐ ์ ์šฉ (24)

(tWRRD_sg = tCWL + tWTR_L + 6)

(tWTR_L = tWRRD_sg - tCWL - 6)


tWTR_S

์ž๋™ ๊ณ„์‚ฐ ์ ์šฉ (12)

(tWRRD_dg = tCWL + tWTR_S + 6)

(tWTR_S = tWRRD_dg - tCWL - 6)


tRDRD_sg 16


tRDRD_dg 8


tRDWR_sg 20


tRDWR_dg 20


tWRWR_sg 12


tWRWR_dg 8


tWRRD_sg 62

tWTR_L ๋ฐ”๊ฟ€ ๋•Œ ์ด ๊ฐ’์„ ๋ฐ”๊ฟ”์ค˜์•ผ ํ•จ

(tWRRD_sg = tCWL + tWTR_L + 6)


tWRRD_dg 50

tWTR_S ๋ฐ”๊ฟ€ ๋•Œ ์ด ๊ฐ’์„ ๋ฐ”๊ฟ”์ค˜์•ผ ํ•จ

(tWRRD_dg = tCWL + tWTR_S + 6)



tRDRD_dr 1 (๋ณด๋“œ์— ๋”ฐ๋ผ์„œ ์ตœ์†Ÿ๊ฐ’ 4)

tRDRD_dd 1 (๋ณด๋“œ์— ๋”ฐ๋ผ์„œ ์ตœ์†Ÿ๊ฐ’ 4)

tRDWR_dr 1 (๋ณด๋“œ์— ๋”ฐ๋ผ์„œ ์ตœ์†Ÿ๊ฐ’ 4)

tRDWR_dd 1 (๋ณด๋“œ์— ๋”ฐ๋ผ์„œ ์ตœ์†Ÿ๊ฐ’ 4)

tWRWR_dr 1 (๋ณด๋“œ์— ๋”ฐ๋ผ์„œ ์ตœ์†Ÿ๊ฐ’ 4)

tWRWR_dd 1 (๋ณด๋“œ์— ๋”ฐ๋ผ์„œ ์ตœ์†Ÿ๊ฐ’ 4)

tWRRD_dr 1 (๋ณด๋“œ์— ๋”ฐ๋ผ์„œ ์ตœ์†Ÿ๊ฐ’ 4)

tWRRD_dd 1 (๋ณด๋“œ์— ๋”ฐ๋ผ์„œ ์ตœ์†Ÿ๊ฐ’ 4)



tWRPRE 49 ๋˜๋Š” 51 *

์‚ฌ์šฉํ•˜๋Š” ๋ฉ”์ธ๋ณด๋“œ, ๋žจ์— ๋”ฐ๋ผ ๊ณ„์‚ฐ ๋ฐฉ๋ฒ•์ด ๋‹ค๋ฆ„

์ˆœ์ • ๊ฐ’ ๋˜๋Š” auto ๊ฐ’ ํ™•์ธ ํ›„ ์ ์šฉํ•  ๊ฒƒ

(tWRPRE = tWRPDEN - 1 or tWRPDEN + 1)


tWRPDEN 50

tWR ๋ฐ”๊ฟ€ ๋•Œ ์ด ๊ฐ’์„ ๋ฐ”๊ฟ”์ค˜์•ผ ํ•จ

(tWRPDEN = tCWL + tWR + 8)