input wire clock,

    input wire SW,

    output reg [1:0]LED = 0

    );


 reg [23:0] clk_cnt;

 reg clk_gen = 0;

     

    always @(posedge clock) begin

        clk_cnt <= clk_cnt + 1'b1;

        if(clk_cnt == 24'd6000_000) begin

            clk_gen <= ~clk_gen;

            clk_cnt <= 24'b0;

        end

    end


    always @(posedge clk_gen) begin

        LED[0] <= ~LED[0];

        if(~SW) LED[1] <= ~LED[1];

    end


베린이라 너무 어려붐....

FPGA에 불들어오게 하는거에요..