module Dlatch (

input wire D,

input wire Gate,

output reg Q,

output reg Qbar

);


always @(*)

if (Gate) Q <= D;


assign Qbar = ~Q;


endmodule 



Error: C:/intelFPGA_lite/18.1/Dlatch.v(11): Register is illegal in left-hand side of continuous assignment 라고 에러 뜨는데 이유를 모르겠어요