library ieee;
use ieee.std_logic_1164.all;

entity f_divison is
 port(clk, d0, d1, d2, d3  : in std_logic;
  f0, f1, f2, f3    : inout std_logic);
end f_divison;

architecture system of f_divison is
 component d_ff is
  port(d, clk   : in std_logic;
   qout, qout_bar : inout std_logic);
 end component;

  signal qb0, qb1, qb2, qb3 : std_logic;
  begin
  f_d0:d_ff
   port map(clk=>clk, qout=>f0, qout_bar=>qb0,
     d=>d0,
     d0<=(qb0 and f1 and f2 and f3) or (f0 and (qb2 or qb3 or qb1)));
  f_d1:d_ff
   port map(clk=>clk, qout=>f1, qout_bar=>qb1,
     d=>d1,
     d1<=(f1 and qb3) or (f1 and qb2) or (qb1 and f2 and f3));
  f_d2:d_ff
   port map(clk=>clk, qout=>f2, qout_bar=>qb2,
     d=>d2,     
     d2<=(qb2 and f3) or (f2 and qb3));
  f_d3:d_ff
   port map(clk=>clk, qout=>f3, qout_bar=>qb3,
     d=>d3,
     d3<=qb3);
end system;

에러가 2개 뜨는데 어디가 잘못된거임 ?