BIOS 중에는 Maximum TLP (Transaction Layer Packet) payload size 라는 항목이 있는 BIOS가 있다.

TLP payload size 는 각 데이타 패킷안의 전송할 데이타 양을 결정하는 파라메터이다.
이 파라메터는 전적으로 메인보드 칩셋의 PCI-E 콘트롤러에 영향을 받는다.


예)

When set to 128, the motherboard chipset\'s PCI Express controller  will only support a maximum data payload of 128 bytes within each  TLP.
When set to 256, the motherboard chipset\'s PCI Express controller  will only support a maximum data payload of 256 bytes within each  TLP.
When set to 512, the motherboard chipset\'s PCI Express controller  will only support a maximum data payload of 512 bytes within each  TLP.
When set to 1024, the motherboard chipset\'s PCI Express controller  will only support a maximum data payload of 1024 bytes within each TLP.
When set to 2048, the motherboard chipset\'s PCI Express controller  will only support a maximum data payload of 2048 bytes within each TLP.




The Max Payload Size and TLP are functions related to the PCI-Express bus
The PCI Express bus uses three \"layers\" of communication (similar to the layers in the OSI Model (http://en.wikipedia.org/wiki/Osi_model)) -- physical, data link, and transaction.

The transaction layer is where all \"real\" communication takes place (the physical layer is the wires, and the data link layer controls/maintains the link between PCI Express devices)
The smallest chunk of data on the transaction layer is known as a \"Transaction Layer Packet\" or TLP (similarly, the smallest chunk of data on the data link layer is known as a \"Data Link Layer Packet\" or DLLP)

A TLP consists of both a header (containing packet information), a payload (containing the actual data to be transmitted), and possibly an ECRC (containing error checking info)
The Max Payload Size sets the maximum size of the payload that any TLP can contain. Devices must be able to recieve payloads that large, and must not send payloads any larger.


TLP size is a negotiated value between the host  system and the endpoint.
Every port in the path from the root port through the switch to the endpoint all have a max payload size.
The link can only support the minimum max payload size  reported down the entire link.
Usually the root port is the link that has the lowest Max TLP size.
PCIe switches usually have a very large Max TLP payload  such as 2048 bytes.
Most endpoints don’t support more than 256 bytes.

Intel x38 chipsets typically have 128byte max payload size.  
Intel x58 chipsets often support 256 by max payload size.

But remember it is  ultimately controlled by the Motherboard BIOS.
So even if you have the chipset,  the manufacturer may not enable it.
Once the value is determined by the BIOS, it will rewrite  this value to every port down the link during link training.
When The GN4124 DMA engine is transferring data, part of  the setup is to copy the value from the PCIE register
containing the negotiated  max payload size to  the BAR0 register 34.
The bar 4 register ultimately determines what size of  data  payload in the TLP  GN4124 will send up to the host.
PCIe Device control register offset  0×60:





Now,  you could put a higher value in there and see what happens, if you exceed the  negotiated value of payload size,
at some point the system will hang as the Root  port cannot handle the incoming data.
One  day I did an experiment on my system in the lab.
The experiment was to determine  how big I can make the data payload before the system crashed.
The  test was simple.

Keep increasing the DMA payload size in register 0×34 starting  with the max negotiated TLP size and
monitor the PCIe traffic throughput and  data payload size and with my trusty Agilent E2960 prｏtｏcｏl  analyzer.
To my  surprise with my starting TLP size was 128 bytes.

At the end of the experiment I  topped out at about 370 byte payload, after that the system always crashed.
That  gave me a throughput of nearly 750 Megabytes per second and a bus efficiency of  95%.
So  Clearly the root ports have some margin for increased throughput.

But I am  certain that every system is different so pushing beyond the negotiated size is  not recommended.
It is akin to CPU Over clocking that PC enthusiasts like to  do.

If you  want to see that number change in a stable way, you really need to change  chipsets to a newer one like Intel X58 or the AMD equivalent.

When TLP set to 4096, the motherboard chipset\'s PCI Express controller  supports the maximum data payload of 4096 bytes within each TLP. This is the  maximum payload size currently supported by the PCI Express prｏtｏcｏl.

It  is recommended that you set this BIOS feature to 4096, as this allows all PCI  Express devices connected to send up to 4096 bytes of data in each TLP. This  gives you maximum efficiency per transfer.

However, this is subject to  the PCI device connected to it. If that device only supports a maximum TLP  payload size of 512 bytes, the motherboard chipset will communicate with it with  a maximum TLP payload size of 512 bytes, even if you set this BIOS feature to  4096.

On the other hand, if you set this BIOS feature to a low value like  256, it will force all connected devices to use a maximum payload size of 256  bytes, even if they support a much larger TLP payload size.