use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prac1 is
Port ( prs : in STD_LOGIC;
clr : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR (7 downto 0);
tseg_c : out std_logic_vector(5 downto 0));
end prac1;
architecture Behavioral of prac1 is
signal rcos1, rcos10, rcom1, rcom10, rcoh1,rcoh10 : std_logic;
signal s1, s10, m1, m10, h1, h10 : std_logic_vector(3 downto 0);
signal seg_c : std_logic_vector(5 downto 0);
begin
process(prs,clr,clk,s1) -- one place of second
begin
if prs = \'0\' then
s1 <= \"1111\";
rcos1 <= \'1\';
elsif clr = \'0\' then
s1 <= \"0000\";
rcos1 <= \'0\';
elsif clk\' event and clk = \'1\' then
if s1 = \"1001\" then
s1 <= \"0000\";
rcos1 <= \'1\';
elsif not (s1 = \"1001\") then
s1 <= s1 + \"0001\";
rcos1 <= \'0\';
end if;
end if;
if seg_c = \"000001\" then
case s1 is
when \"0000\" =>seg<= \"11000000\"; --0
when \"0001\" =>seg<= \"11111001\"; --1
when \"0010\" =>seg<= \"10100100\"; --2
when \"0011\" =>seg<= \"10110000\"; --3
when \"0100\" =>seg<= \"10011001\"; --4
when \"0101\" =>seg<= \"10010010\"; --5
when \"0110\" =>seg<= \"10000010\"; --6
when \"0111\" =>seg<= \"11011000\"; --7
when \"1000\" =>seg<= \"10000000\"; --8
when \"1001\" =>seg<= \"10010000\"; --9
when others =>seg<= \"01111111\"; -- error is dot(.)
end case;
end if;
end process;
process(prs,clr,rcos1,s10) -- ten place of second
begin
if prs = \'0\' then
s10 <= \"1111\";
rcos10 <= \'1\';
elsif clr = \'0\' then
s10 <= \"0000\";
rcos10 <= \'0\';
elsif rcos1\' event and rcos1 = \'1\' then
if s10 = \"0101\" then
s10 <= \"0000\";
rcos10 <= \'1\';
elsif not (s10 = \"0101\") then
s10 <= s10 + \"0001\";
rcos10 <= \'0\';
end if;
end if;
if seg_c = \"000010\" then
case s10 is
when \"0000\" =>seg<= \"11000000\"; --0
when \"0001\" =>seg<= \"11111001\"; --1
when \"0010\" =>seg<= \"10100100\"; --2
when \"0011\" =>seg<= \"10110000\"; --3
when \"0100\" =>seg<= \"10011001\"; --4
when \"0101\" =>seg<= \"10010010\"; --5
when \"0110\" =>seg<= \"10000010\"; --6
when \"0111\" =>seg<= \"11011000\"; --7
when \"1000\" =>seg<= \"10000000\"; --8
when \"1001\" =>seg<= \"10010000\"; --9
when others =>seg<= \"01111111\"; -- error is dot(.)
end case;
end if;
end process;
process(prs,clr,rcos10,m1) -- one place of minute
begin
if prs = \'0\' then
m1 <= \"1111\";
rcom1 <= \'1\';
elsif clr = \'0\' then
m1 <= \"0000\";
rcom1 <= \'0\';
elsif rcos10\' event and rcos10 = \'1\' then
if m1 = \"1001\" then
m1 <= \"0000\";
rcom1 <= \'1\';
elsif not (m1 = \"1001\") then
m1 <= m1 + \"0001\";
rcom1 <= \'0\';
end if;
end if;
if seg_c = \"000100\" then
case m1 is
when \"0000\" =>seg<= \"11000000\"; --0
when \"0001\" =>seg<= \"11111001\"; --1
when \"0010\" =>seg<= \"10100100\"; --2
when \"0011\" =>seg<= \"10110000\"; --3
when \"0100\" =>seg<= \"10011001\"; --4
when \"0101\" =>seg<= \"10010010\"; --5
when \"0110\" =>seg<= \"10000010\"; --6
when \"0111\" =>seg<= \"11011000\"; --7
when \"1000\" =>seg<= \"10000000\"; --8
when \"1001\" =>seg<= \"10010000\"; --9
when others =>seg<= \"01111111\"; -- error is dot(.)
end case;
end if;
end process;
process(prs,clr,rcom1,m10) -- ten place of minute
begin
if prs = \'0\' then
m10 <= \"1111\";
rcom10 <= \'1\';
elsif clr = \'0\' then
m10 <= \"0000\";
rcom10 <= \'0\';
elsif rcom1\' event and rcom1 = \'1\' then
if m10 = \"0101\" then
m10 <= \"0000\";
rcom10 <= \'1\';
elsif not (m10 = \"0101\") then
m10 <= m10 + \"0001\";
rcom10 <= \'0\';
end if;
end if;
if seg_c = \"001000\" then
case m10 is
when \"0000\" =>seg<= \"11000000\"; --0
when \"0001\" =>seg<= \"11111001\"; --1
when \"0010\" =>seg<= \"10100100\"; --2
when \"0011\" =>seg<= \"10110000\"; --3
when \"0100\" =>seg<= \"10011001\"; --4
when \"0101\" =>seg<= \"10010010\"; --5
when \"0110\" =>seg<= \"10000010\"; --6
when \"0111\" =>seg<= \"11011000\"; --7
when \"1000\" =>seg<= \"10000000\"; --8
when \"1001\" =>seg<= \"10010000\"; --9
when others =>seg<= \"01111111\"; -- error is dot(.)
end case;
end if;
end process;
process(prs,clr,rcom10,h1) -- one place of hour
begin
if prs = \'0\' then
h1 <= \"1111\";
rcoh1 <= \'1\';
elsif clr = \'0\' then
h1 <= \"0000\";
rcoh1 <= \'0\';
elsif rcom10\' event and rcom10 = \'1\' then
if h1 = \"0011\" then
h1 <= \"0000\";
rcoh1 <= \'1\';
elsif not (h1 = \"0011\") then
h1 <= h1 + \"0001\";
rcoh1 <= \'0\';
end if;
end if;
if seg_c = \"010000\" then
case h1 is
when \"0000\" =>seg<= \"11000000\"; --0
when \"0001\" =>seg<= \"11111001\"; --1
when \"0010\" =>seg<= \"10100100\"; --2
when \"0011\" =>seg<= \"10110000\"; --3
when \"0100\" =>seg<= \"10011001\"; --4
when \"0101\" =>seg<= \"10010010\"; --5
when \"0110\" =>seg<= \"10000010\"; --6
when \"0111\" =>seg<= \"11011000\"; --7
when \"1000\" =>seg<= \"10000000\"; --8
when \"1001\" =>seg<= \"10010000\"; --9
when others =>seg<= \"01111111\"; -- error is dot(.)
end case;
end if;
end process;
process(prs,clr,rcoh1,h10) -- ten place of hour
begin
if prs = \'0\' then
h10 <= \"1111\";
rcoh10 <= \'1\';
elsif clr = \'0\' then
h10 <= \"0000\";
rcoh10 <= \'0\';
elsif rcoh1\' event and rcoh1 = \'1\' then
if h10 = \"0001\" then
h10 <= \"0000\";
rcoh10 <= \'1\';
elsif not (h10 = \"0001\") then
h10 <= h10 + \"0001\";
rcoh10 <= \'0\';
end if;
end if;
if seg_c = \"100000\" then
case h10 is
when \"0000\" =>seg<= \"11000000\"; --0
when \"0001\" =>seg<= \"11111001\"; --1
when \"0010\" =>seg<= \"10100100\"; --2
when \"0011\" =>seg<= \"10110000\"; --3
when \"0100\" =>seg<= \"10011001\"; --4
when \"0101\" =>seg<= \"10010010\"; --5
when \"0110\" =>seg<= \"10000010\"; --6
when \"0111\" =>seg<= \"11011000\"; --7
when \"1000\" =>seg<= \"10000000\"; --8
when \"1001\" =>seg<= \"10010000\"; --9
when others =>seg<= \"01111111\"; -- error is dot(.)
end case;
end if;
end process;
process(clk)
begin
if clk\' event and clk = \'1\' then
seg_c <= seg_c(4 downto 0) & seg_c(5);
end if;
end process;
tseg_c <= seg_c;
end Behavioral;
seg라는 값이 멀티 소스라는 오류가 뜨네요 seg라는 출력에 다양한 상황에 맞는 출력을 내보내려면 어떻게해야하나요..
성님들 도와주세요 VHDL 혼자 공부하려니 너무 어렵네요.. ㅠㅠ