실습실 컴으로 하다보면
같은 코든데 가끔 디스플레이가 안되고 그러는게 있거든
지금 내 노트북에서 디스플레이가 안되는데
디스플레이좀 봐줄수 있어? ㅠㅠ $display 가 아예 밑 노티스콘솔?창에 안나와
디스플레이 나오면 0~4095까지 나와야하고 2188번째에 correct 되나 봐봐줘방..
//11111
`timescale 1 ns/1 ns
module Code_Detector(Start, Red, Green, Blue, Clk, Rst, U);
input Start, Red, Green, Blue;
output reg U;
input Clk, Rst;
parameter Wait_state = 0, Start_state = 1, Red1_state = 2, Blue_state = 3,
Green_state = 4, Red2_state = 5; //don't need to 110, 111
reg [2:0] State, StateNext;
// StateReg
always @(posedge Clk) begin
if (Rst == 1 )
State <= Wait_state;
else
State <= StateNext;
end // StateReg end
// CombLogic
always @(Start, Red, Green, Blue, State)
begin
U <= 0;
case(State)
Wait_state: begin
U <= 0;
if (Start == 0)
StateNext <= Wait_state;
else
StateNext <= Start_state;
end
Start_state: begin
U <= 0;
if (Red == 1 && Green == 0 && Blue == 0)
StateNext <= Red1_state;
else if (Red == 1 && Green == 1 && Blue == 1)
StateNext <= Start_state;
else//b+g
begin
StateNext <= Wait_state;
end
end
Red1_state: begin
U <= 0;
if (Red == 0 && Green == 0 && Blue == 1)
StateNext <= Blue_state;
else if (Red == 1 && Green == 1 && Blue == 1)
StateNext <= Red1_state;
else
StateNext <= Wait_state;
end
Blue_state: begin
U <= 0;
if (Red == 0 && Green == 1 && Blue == 0)
StateNext <= Green_state;
else if (Red == 1 && Green == 1 && Blue == 1)
StateNext <= Blue_state;
else
StateNext <= Wait_state;
end
Green_state: begin
U <= 0;
if (Red == 1 && Green == 0 && Blue == 0)
StateNext <= Red2_state;
else if (Red == 1 && Green == 1 && Blue == 1)
StateNext <= Green_state;
else
StateNext <= Wait_state;
end
Red2_state: begin
U <= 1;
StateNext <= Wait_state;
end
default: begin //don't use 110, 111
U <= 0;
StateNext <= Wait_state;
end
endcase //case end
end// CombLogic end
endmodule
!! 파일 2개야 따로 만들어야해 테스트벤치
//2222
//code_detector_TB.v
`timescale 1 ns/1 ns
module Testbench();
reg Start_s, Red_s, Green_s, Blue_s, Clk_s, Rst_s;
reg [12:0] Answer_Index;
reg [12:0] Index; //12bits 4096 test input
wire U_s;
Code_Detector CompToTest(Start_s, Red_s, Green_s, Blue_s, Clk_s, Rst_s, U_s);
// Clock Procedure
always begin
Clk_s <= 0;
#10;
Clk_s <= 1;
#10;
end
// Vector Procedure
initial begin
Rst_s <= 1;
Start_s <= 0; //now start state
Index <= 12'b000_000_000_000;
@(posedge Clk_s);
for(Index=0; Index<13'b1000_000_000_000; Index=Index+13'b0000_000_000_001) begin // 0~4096
Rst_s <= 0;
Start_s <= 1;
@(posedge Clk_s);
#5;
Red_s <= Index[2];
Green_s <= Index[1];
Blue_s <= Index[0];
@(posedge Clk_s);
#5;
Red_s <= Index[5];
Green_s <= Index[4];
Blue_s <= Index[3];
@(posedge Clk_s);
#5;
Red_s <= Index[8];
Green_s <= Index[7];
Blue_s <= Index[6];
@(posedge Clk_s);
#5;
Red_s <= Index[11];
Green_s <= Index[10];
Blue_s <= Index[9];
@(posedge Clk_s);
#5;
if (U_s == 1) begin // print correct case
$display("# %d: %b is correct", Index, Index);
Answer_Index <= Index;
@(posedge Clk_s);
#5;
end
else begin // print incorrect case
$display("# %d: %b is incorrect", Index, Index);
@(posedge Clk_s);
#5;
end
end // end for loop
$stop;
$display("# %d: %b is correct", Answer_Index, Answer_Index);
end
endmodule
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