module four_reg (clk,in,rst,q);

input [3:0] in;

input clk,rst;

output [3:0] q;

reg [3:0] a;

always @(posedge clk, negedge rst)

begin

if(~rst)

a<=4'b 0000;

else

a<=in;

end

assign q=a;

endmodule


이 모듈에

`timescale 1 ns/1 ps
module tfour_reg;
reg [3:0] in;
reg clk,rst;
wire [3:0] q;
four_reg im(.in(in), .clk(clk), .rst(rst), .q(q));
always #100 clk = ~clk;
always #1600 rst = ~rst;
initial begin
clk<=0;rst<=1;
in<=4'b 0000; #100;
in<=4'b 0001; #100;
in<=4'b 0010; #100;
in<=4'b 0011; #100;
in<=4'b 0100; #100;
in<=4'b 0101; #100;
in<=4'b 0110; #100;
in<=4'b 0111; #100;
in<=4'b 1000; #100;
in<=4'b 1001; #100;
in<=4'b 1010; #100;
in<=4'b 1011; #100;
in<=4'b 1100; #100;
in<=4'b 1101; #100;
in<=4'b 1110; #100;
in<=4'b 1111; #100;
end
endmodule

이 테스트벤치를 줬는데 q[0]이 계속 0이 뜨는 이유점 알려줘여