| Bit Logic Instructions | |
| A bit | And |
| AN bit | And Not |
| O bit | Or |
| ON bit | Or Not |
| X bit | Exclusive Or |
| XN bit | Exclusive Or Not |
| O | And before Or |
| A( | And with Nesting Open |
| AN( | And Not with Nesting Open |
| O( | Or with Nesting Open |
| ON( | Or Not with Nesting Open |
| X( | Exclusive Or with Nesting Open |
| XN( | Exclusive Or Not with Nesting Open |
| ) | Nesting Closed |
| = bit | Assign |
| R bit | Reset |
| S bit | Set |
| NOT | Negate RLO |
| SET | Set RLO (=1) |
| CLR | Clear RLO (=0) |
| SAVE | Save RLO in BR Register |
| FN bit | Edge Negative |
| FP bit | Edge Positive |
| Comparison Instructions | |
| ==I,D,R | ACCU2 is equal to ACCU1 |
| <>I,D,R | ACCU2 is not equal to ACCU1 |
| >I,D,R | ACCU2 is greater than ACCU1 |
| <I,D,R | ACCU2 is less than ACCU1 |
| >=I,D,R | ACCU2 is greater than or equal to ACCU1 |
| <=I,D,R | ACCU2 is less than or equal to ACCU1 |
| I Integer (16-Bit) | |
| D Double Integer (32-Bit) | |
| R Floating-Point Number (32-Bit)=Real | |
| Conversion Instructions | |
| BTI | BCD to Integer |
| ITB | Integer to BCD |
| BTD | BCD to Double Integer |
| ITD | Integer to Double Integer |
| DTB | Double Integer to BCD |
| DTR | Double Integer to Floating-Point |
| INVI | Ones Complement Integer |
| INVD | Ones Complement Double Integer |
| NEGI | Twos Complement Integer |
| NEGD | Twos Complement Double Integer |
| NEGR | Negate Floating-Point Number |
| CAW | Change Byte Sequence in ACCU 1-L (16-Bit) |
| CAD | Change Byte Sequence in ACCU 1 (32-Bit) |
| RND | Round |
| TRUNC | Truncate |
| RND+ | Round to Upper Double Integer |
| RND- | Round to Lower Double Integer |
| Counter Instructions | |
| FR Cx | Enable Counter (Free) |
| L C#n | Preset Counter Value Count Format, number= 0 ~ 999 |
| L W#16#txyz | Preset Counter Value BCD Format |
| L Cx | Load Current Counter Value into ACCU 1 |
| LC Cx | Load Current Counter Value into ACCU 1 as BCD |
| R Cx | Reset Counter |
| S Cx | Set Counter Preset Value |
| CU Cx | Counter Up |
| CD Cx | Counter Down |
| Data Block Instructions | |
| OPN DBx | Open a Shared DB |
| OPN DIx | Open a Instance DB |
| CDB | Exchange Shared DB and Instance DB |
| L DBLG | Load Length of Shared DB in ACCU 1 |
| L DBNO | Load Number of Shared DB in ACCU 1 |
| L DILG | Load Length of Instance DB in ACCU 1 |
| L DINO | Load Number of Instance DB in ACCU 1 |
| Logic Control Instructions | |
| JU Label | Jump Unconditional |
| JL Label | Jump to Labels |
| JC Label | Jump if RLO = 1 |
| JCN Label | Jump if RLO = 0 |
| JCB Label | Jump if RLO = 1 with BR |
| JNB Label | Jump if RLO = 0 with BR |
| JBI Label | Jump if BR = 1 |
| JNBI Label | Jump if BR = 0 |
| JO Label | Jump if OV = 1 |
| JOS Label | Jump if OS = 1 |
| JZ Label | Jump if Zero |
| JN Label | Jump if Not Zero |
| JP Label | Jump if Plus |
| JM Label | Jump if Minus |
| JPZ Label | Jump if Plus or Zero |
| JMZ Label | Jump if Minus or Zero |
| JUO Label | Jump if Unordered |
| LOOP Label | Loop |
| Label : | Label |
| Integer Math Instructions | |
| +I | Add ACCU 1 and ACCU 2 as Integer |
| -I | Subtract ACCU 1 from ACCU 2 as Integer |
| *I | Multiply ACCU 1 and ACCU 2 as Integer |
| /I | Divide ACCU 2 by ACCU 1 as Integer |
| +constant | Add Integer Constant , Double Integer Constant |
| +D | Add ACCU 1 and ACCU 2 as Double Integer |
| -D | Subtract ACCU 1 from ACCU 2 as Double Integer |
| *D | Multiply ACCU 1 and ACCU 2 as Double Integer |
| /D | Divide ACCU 2 by ACCU 1 as Double Integer |
| MOD | Division Remainder Double Integer |
| Floating-Point Math Instructions | |
| +R | Add ACCU 1 and ACCU2 , accu1=accu2+accu1 |
| -R | Subtract ACCU 1 from ACCU 2, accu1=accu2-accu1 |
| *R | Multiply ACCU 1 and ACCU, accu1=accu2*accu1 |
| /R | Divide ACCU 2 by ACCU 1, accu1=accu2/accu1 |
| ABS | Absolute Value |
| SQR | Generate the Square |
| SQRT | Generate the Square Root |
| EXP | Generate the Exponential Value |
| LN | Generate the Natural Logarithm |
| SIN | Generate the Sine of Angles |
| COS | Generate the Cosine of Angles |
| TAN | Generate the Tangent of Angles |
| ASIN | Generate the Arc Sine |
| ACOS | Generate the Arc Cosine |
| ATAN | Generate the Arc Tangent |
| Load and Transfer Instructions | |
| L address | Load Byte,Word, Dword, constant |
| L STW | Load Status Word into ACCU 1 |
| LAR1 AR2 | Load Address Register 1 from Address Register 2 |
| LAR1 P#y.x(or P#Zy.x) | Load Address Register 1 with Area Pointer |
| LAR1 P##local variable | Load Address Register 1 with Local Varible Name |
| LAR1 | Load Address Register 1 from ACCU 1 |
| LAR2 P#y.x(or P#Zy.x) | Load Address Register 2 with Area Pointer |
| LAR2 P##local variable | Load Address Register 2 with Local Varible Name |
| LAR2 | Load Address Register 2 from ACCU 1 |
| T address | Transfer |
| T STW | Transfer ACCU 1 into Status Word |
| TAR1 AR2 | Transfer Address Register 1 to Address Register 2 |
| TAR1 <D> | Transfer Address Register 1 to Destination (32-Bit Pointer) |
| TAR2 <D> | Transfer Address Register 2 to Destination (32-Bit Pointer) |
| TAR1 | Transfer Address Register 1 to ACCU 1 |
| TAR2 | Transfer Address Register 2 to ACCU 1 |
| CAR | Exchange Address Register 1 with Address Register 2 |
| Program Control Instructions | |
| BE | Block End |
| BEC | Block End Conditional |
| BEU | Block End Unconditional |
| CALL | Block Call |
| CC FBx, CC FCx | Conditional Call |
| UC FBx, UC FCx | Unconditional Call |
| Call FBx,DBy | |
| Call FCx | |
| Call SFBx, DBy | |
| Call SFCx | |
| CALL # variable name | Call Multiple Instance |
| MCR( | Save RLO in MCR Stack, Begin MCR |
| )MCR | End MCR |
| MCRA | Activate MCR Area |
| MCRD | Deactivate MCR Area |
| Shift Instructions | |
| SSI , SSI n | Shift Sign Integer, number=0~15 |
| SSD , SSD n | Shift Sign Double Integer, number=0~32 |
| SLW , SLW n | Shift Left Word, number=0~15 |
| SRW , SRW n | Shift Right Word, number=0~15 |
| SLD , SLD n | Shift Left Double Word, number=0~32 |
| SRD , SRD n | Shift Right Double Word, number=0~32 |
| Rotate Instructions | |
| RLD , RLD n | Rotate Left Double Word, number=0~32 |
| RRD , RRD n | Rotate Right Double Word, number=0~32 |
| RLDA | Rotate ACCU 1 Left via CC 1 |
| RRDA | Rotate ACCU 1 Right via CC 1 |
| Timer Instructions | |
| FR Tx | Enable Timer (Free) |
| L S5T#aHbMcSdMS | Preset Timer Value S5time Format |
| L w#16#txyz | Preset Timer Value BCD Format |
| L Tx | Load Current Timer Value into ACCU 1 as Integer |
| LC Tx | Load Current Timer Value into ACCU 1 as BCD |
| R Tx | Reset Timer |
| SD Tx | On-Delay Timer |
| SE Tx | Extended Pulse Timer |
| SF Tx | Off-Delay Timer |
| SP Tx | Pulse Timer |
| SS Tx | Stored On-Delay Timer |
| Word Logic Instructions | |
| AW ,AW constant | AND Word, constant=Word,16-bit constant |
| OW ,OW constant | OR Word, constant=Word,16-bit constant |
| XOW ,XOW constant | Exclusive OR Word, constant=Word,16-bit constant |
| AD ,AD constant | AND Double Word, constant=Dword,32-bit constant |
| OD ,OD constant | OR Double Word, constant=Dword,32-bit constant |
| XOD ,XOD constant | Exclusive OR Double Word, constant=Dword,32-bit constant |
| Accumulator and Address Register Instructions | |
| TAK | Toggle ACCU 1 with ACCU 2 |
| PUSH | CPU with Two ACCUs |
| PUSH | CPU with Four ACCUs |
| POP | CPU with Two ACCUs |
| POP | CPU with Four ACCUs |
| ENT | Enter ACCU Stack |
| LEAVE | Leave ACCU Stack |
| INC n | Increment ACCU 1-L-L , n=0~255 |
| DEC n | Decrement ACCU 1-L-L, n=0~255 |
| +AR1 | Add ACCU 1 to Address Register 1, AR1=AR1+ACCU1 |
| +AR2 | Add ACCU 1 to Address Register 2, AR2=AR2+ACCU1 |
| BLD | Program Display Instruction (Null) |
| NOP 0 | Null Instruction |
| NOP 1 | Null Instruction |
| CAW | Change Byte Sequence in ACCU 1-L (16-Bit) |
| CAD | Change Byte Sequence in ACCU 1 (32-Bit) |
| +AR1 P#y.x | AR1=AR1+P#y.x |
| +AR2 P#y.x | AR2=AR2+P#y.x |
| Status Word | |
| BR | Binary Result Bit |
| SAVE | Save RLO in BR Bit |
| ==0 | Scan for ((CC 1 = 0) AND (CC 0 = 0)) |
| <>0 | Scan for (((CC 1 = 1) AND (CC 0 = 0)) OR ((CC 1 = 0) AND (CC 0 = 1))) |
| >0 | Scan for ((CC 1 = 1) AND (CC 0 = 0)) |
| <0 | Scan for ((CC 1 = 0) AND (CC 0 = 1)) |
| >=0 | Scan for (((CC 1 = 1) AND (CC 0 = 0)) OR ((CC 1 = 0) AND (CC 0 = 0))) |
| <=0 | Scan for (((CC 1 = 0) AND (CC 0 = 1)) OR ((CC 1 = 0) AND (CC 0 = 0))) |
| UO | Scan for ((CC 1 = 1) AND (CC 0 = 1)), UnOrder |
| OV | Overflow |
| OS | Overflow Stored |
| +P#y.x | |
| Word Indirect Address | |
| L number T MWx LWx DBWx DIWx OPN DB[MWx] |
number
=0 ~ 65,535 Word Area T, C, DB, FB, FC[Word Area] |
| Ex1) L +5 T MW2 OPN DB[MW2] |
|
| Ex2) OPN DB10 L +20 T DBW10 A T[DBW10] |
|
| Dword Indrect Address | |
| ex1) L P#y.x T MDx A I [MDx] = Q [MDx] |
T MDx LDx DBDx DIDx |
| ex2) L P#y.x T MDx L IB [MD2x] T MW [MDx] |
T MDx LDx DBDx DIDx |
| Area-Internal Register Indirect Addressing | |
| ex1) L P#y.z LAR1 A I [AR1, P#y.z] = Q [AR1, P#y.z] |
|
| ex2)L P#y.x LAR2 L IB [AR2, P#y.x] T MW[AR2,P#y.x] |
|
| Area-Crossing Register Indirect Addressing | |
| ex1)L P#Zy.x LAR1 L P#Zy.x LAR2 A [AR1, P#y.x] = [AR2, P#y.x] |
|
| ex2)L P#Zy.x LAR2 L P#Zy.x LAR1 L B [AR2, P#y.x] T W [AR1, P#y.x] |
|
| Data Type and range | |
| BOOL | FALSE,TRUE(1bit) |
| BYTE | B#16#00~B#16#FF, 16#00~16#FF |
| CHAR | ‘A’ |
| WORD | W#16#0000~W#16#FFFF, 16#0000~16#FFFF |
| 2#0000_0000_0000_0000~2#1111_1111_1111_1111 | |
| C#000 C#999 | |
| B#(0,0) B#(255,255) | |
| DWORD | DW#16#0000_0000~DW#16#FFFF_FFFF |
| 16#0000_0000~16#FFFF_FFFF | |
| 2#0000_0000_..._0000_0000~2#1111_1111_..._1111_1111 | |
| B#(0,0,0,0)~B#(255,255,255,255) | |
| INT | -32768~+32767 |
| DINT | L#-2147483648~L#+2 147 483 647 |
| REAL | Upper limit +/-3.402823e+38 ~ Lower limit +/-1.175495e-38 |
| S5TIME | S5T#0ms~S5T#2h46m30s |
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