xilinx 프로그램으로 vhdl 4비트 카운터를 작성해야되는데 컴포넌트 포트맵 괄호에 어떻게 넣어야 되지..?ㅠ



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity counter is
port ( Y : in std_logic_vector(3 downto 0);
clock, clear, cin : in std_logic;
sum : out std_logic_vector(3 downto 0);
cout : out std_logic
);
end counter;

architecture Behavioral of counter is
component DFF
port( D : in std_logic_vector(3 downto 0);
Clk, Clr : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end component;
component fourFA
port( A, B : in std_logic_vector(3 downto 0);
ci : in std_logic;
s : out std_logic_vector(3 downto 0);
co : out std_logic
);
end component;
signal databus, x : std_logic_vector(3 downto 0);
begin
memory : DFF port map(???); --이부분
Adder : fourFA port map( ???); --이부분
sum <= x;
end Behavioral;