library IEEE;
use IEEE.std_logic_1164.all;
entity multi is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
p : out STD_LOGIC_VECTOR(7 downto 0)
);
end multi;
architecture hard of multi is
begin
process(a,b)
variable pv,bp : STD_LOGIC_VECTOR(7 downto 0);
begin
pv :="00000000";
bp :="0000"&b;
for i in 0 to 2 loop
if a(i) = '1' then
pv := pv or bp;
end if;
bp := bp(6 downto 0) & '0';
end loop;
p <= pv or ((not b) or "0001")&"0000";
end process;
end hard;
라는 코드고 컴파일 오류없어서 이제 시뮬레이션 단계인데
테스트 벤치법에대해 배우질못해서 구글링을하다가 방법에 껴맞춰서 했는데
library IEEE;
use IEEE.std_logic_1164.all;
entity multit is
end multit;
architecture hardt of multit is
begin
process(a,b)
variable pv,bp : STD_LOGIC_VECTOR(7 downto 0);
begin
pv :="00000000";
wait for 50ns;
bp :="0000"&b;
wait for 50ns;
for i in 0 to 2 loop
if a(i) = '1' then
pv := pv or bp;
wait for 50ns;
end if;
bp := bp(6 downto 0) & '0';
wait for 50ns;
end loop;
p <= pv or ((not b) or "0001")&"0000";
wait for 50ns;
end process;
end hardt;
이렇게 하는게 원래 코드의 테스트벤치를 위한 코딩이 맞을까 ?
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