우리집 VHDL modelsim이 이상한데 테스트벤치한번만 시뮬좀..ㅠㅠ

[이건머야(222.238)]

library IEEE;

use IEEE.std_logic_1164.all;

entity multit is

end multit;

architecture hard of test is

port(

a : in STD_LOGIC_VECTOR(3 downto 0);

b : in STD_LOGIC_VECTOR(3 downto 0);

p : out STD_LOGIC_VECTOR(7 downto 0)

    );

begin

process(a,b)

variable pv,bp : STD_LOGIC_VECTOR(7 downto 0);

begin

pv :="00000000";

wait for 50ns;

bp :="0000"&b;

wait for 50ns;

for i in 0 to 2 loop

if a(i) = '1' then

pv := pv or bp;

wait for 50ns;

end if;

bp := bp(6 downto 0) & '0';

wait for 50ns;

end loop;

p <= pv or ((not b) or "0001")&"0000";

wait for 50ns;

end process;

end hard;

이거 시뮬한번만 돌려주실분 ㅠㅠㅠ

집컴터가 이상함 .. 모델심자체가 안넘어가짐..