module traffic_be(clk,rst,Sa,Sb,La,Lb,state);
input clk,rst,Sa,Sb;
input state;
output [2:0] La,Lb;
reg [2:0] La,Lb;
always@(posedge clk)
if(rst==1) begin
La <= 3'b000;
Lb <= 3'b000;
end
else begin
state <= state+1;
end
always@(state)
begin
case(state)
1'd1, 1'd2, 1'd3, 1'd4:
begin
La <= 3'b100;
Lb <= 3'b001;
state <= state+1;
end
1'd5:
if(Sb==1) begin
La <= 3'b100;
Lb <= 3'b001;
state <= state+1;
end
else begin
La <= 3'b100;
Lb <= 3'b001;
state <= state;
end
1'd6:
begin
La <= 3'b010;
Lb <= 3'b001;
state <= state+1;
end
1'd7, 1'd8, 1'd9, 1'd10:
begin
La <= 3'b001;
Lb <= 3'b100;
state <= state+1;
end
1'd11:
if(Sa==1) begin
La <= 3'b001;
Lb <= 3'b100;
state <= state+1;
end
else begin
La <= 3'b001;
Lb <= 3'b100;
state <= state;
end
1'd12:
begin
La <= 3'b001;
Lb <= 3'b010;
state <= 1'd1;
end
endcase
endmodule
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